1. Field of the Invention
The present invention generally relates to a method of fabricating a chip package, in particular, to a method of fabricating a chip package with a lead frame.
2. Description of Related Art
In the semiconductor industry, the fabrication of integrated circuits (IC) can be divided into three major stages: IC design stage, IC process stage and IC package stage.
In the fabrication of IC, the steps of producing a chip include at least wafer fabrication, IC formation and wafer sawing. The wafer has an active surface, in which active elements are formed. After the fabrication of IC in the wafer is completed, a plurality of bonding pads is disposed on the active surface of the wafer so that the chip subsequently cut out from the wafer can be electrically connected to a carrier through the bonding pads. The carrier is a lead frame or a package substrate, for example. The chip can be connected to the carrier by wire bonding or flip-chip bonding so that the bonding pads of the chip can be electrically connected to the contacts of the carrier to form a chip package.
FIG. 1 is a top view of a conventional chip package. FIG. 2 is a schematic cross-sectional view of the chip package in FIG. 1. As shown in FIGS. 1 and 2, the encapsulant 140 of the package is transparent and the profile of the encapsulant 140 is drawn using dash lines to facilitate subsequent description. The chip package 100 includes a lead frame 110, a chip 120, a plurality of first bonding wires 130, a plurality of second bonding wires 132, a plurality of third bonding wires 134 and an encapsulant 140. The lead frame 110 includes a die pad 112, a plurality of inner leads 114 and a plurality of bus bars 116. The inner leads 114 are disposed outside the die pad 112. The bus bars 116 are disposed between the die pad 112 and the inner leads 114.
The chip 120 has an active surface 122 and a back surface 124 on the opposite side. The chip 120 is disposed on the die pad 112 such that the back surface 124 faces the die pad 112. Furthermore, the chip 120 has a plurality of grounded contacts 126 and a plurality of non-grounded contacts 128. The non-grounded contacts 128 include a plurality of power contacts and a plurality of signal contacts. Both the grounded contacts 126 and the non-grounded contacts 128 are disposed on the active surface 122.
The first bonding wires 130 electrically connect the grounded contacts 126 to the bus bars 116. The second bonding wires 132 electrically connect the bus bars 116 to the grounded leads of the inner leads 114. The third bonding wires 134 electrically connect the other inner leads 114 to corresponding second contacts 128. The encapsulant 140 encapsulates the die pad 112, the inner leads 114, the bus bars 116, the chip 120, the first bonding wires 130, the second bonding wires 132 and the third bonding wires 134.
It should be noted that the process of forming a conventional chip package 100 requires the use of a patterned lead frame. Therefore, the lead frame 110 must include a die pad 112, a plurality of inner leads 114 and a plurality of bus bars 116. Because expensive exposure and development masks are required to pattern the lead frame, the cost for fabricating the lead frame is increased.